News

Next On-Site Seminar on 11.02.2026, CISPA D1, Room 0.15

Written on 04.02.26 (last change on 06.02.26) by Xinyi Xu

Dear All,


The next seminar(s) will take place on 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany) - D1_Room_0.15. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person… Read more

Dear All,


The next seminar(s) will take place on 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany) - D1_Room_0.15. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person as well.

For presenters,
1. We would book the room half an hour in advance, so you are encouraged to arrive a few minutes early to set up your own poster.
2. For this session, you need to print the poster on your own. The size of the poster should be 116x86cm or 86x116cm. You can use the poster printing service of Saarland University (https://www.uni-saarland.de/en/page/uds-card/functions/printing.html -> Posterdruck A0).
3. You need to present your poster in a much smaller group, but you are encouraged to roam around and ask questions about other posters.
4. We encourage you to bring your laptop to present your demo; there will be small tables in the room where you can put your laptop.
 

 

Presenters: Arthur Sanin, Megha Maria Akash, Finn Martin Haderstorfer, Muhammad Azeem Lodhi, Sara-Elena Vatavu, Gunnar Heide, Niklas Beierl, Davide Bombelli, Christian Boseck

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

Presenter: Arthur Sanin

Type of Poster: Master Intro

Advisor: Markus Bläser

Title: Implementation and Empirical Evaluation of Reasoning with c-Representations for Weakly Consistent Belief Bases

Research Area: RA7: Others

Abstract: Nonmonotonic reasoning extends classical logic by defeasible statements of the form ""if A then usually B"", so-called conditionals. A finite set of these conditionals is called a belief base. Nonmonotonic reasoning is about assigning an inductive inference operator to such belief bases. A prominent inductive inference operator is the skeptical c-inference, which takes into account all c-representations of the belief base. Current implementations are limited by the fact that all interpretations must be somewhat plausible, satisfying a notion called 'strong consistency'. We extend the current state-of-the-research implementation by reasoning with c-inference on 'weakly consistent' belief bases, which allow some worlds to be strictly infeasible, thus allowing to not only express plausible beliefs, but also allowing to express facts.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Megha Maria Akash

Type of Poster: Master Intro

Advisor: Mario Fritz, Tejumade Afonja

Title: Activation Steering for Constraint-Faithful Synthetic Tabular Data Generation

Research Area: RA2: Trustworthy Information Processing

Abstract: Synthetic tabular data enables privacy-preserving data sharing in sensitive domains such as healthcare and finance, but existing generative methods based on diffusion models, GANs, and large language models (LLMs) often violate basic constraints such as column types, valid ranges, and relationships between attributes (e.g., generating Age = 5 with Employed = True), which undermines data utility. Although post-processing can filter invalid records, it frequently disrupts the correlations that make synthetic data useful. Motivated by recent advances in activation steering, which show that steering internal model activations along interpretable directions can improve instruction following without retraining, this thesis investigates whether activation steering can improve constraint-following in LLM-based synthetic tabular data generation. The study aims to identify internal activation directions associated with constraint adherence and evaluate whether steering along these directions produces more schema-consistent data while preserving learned distributions.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Finn Martin Haderstorfer

Type of Poster: Bachelor Intro

Advisor: Michael Schwarz

Title: Badram on SO-DIMM

Research Area: RA7: Others

Abstract: The growing adoption of cloud computing raises pressing concerns about trust and data privacy. Trusted Execution Environments (TEEs) have been proposed as promising solutions that implement strong access control and transparent memory encryption within the CPU. While initial TEEs, like Intel SGX, were constrained to small isolated memory regions, the trend is now to protect full virtual machines, e.g., with AMD SEV-SNP, Intel TDX, and Arm CCA. In this paper, we challenge the trust assumptions underlying scaled-up memory encryption and show that an attacker with brief physical access to the embedded SPD chip can cause aliasing in the physical address space, circumventing CPU access control mechanisms. We devise a practical, low-cost setup to create aliases in DDR4 and DDR5 memory modules, breaking the newly introduced integrity guarantees of AMD SEV-SNP. In conclusion, our findings dismantle security guarantees in the SEV-SNP ecosystem, necessitating AMD firmware patches, and nuance DRAM trust assumptions for scalable TEE designs.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Muhammad Azeem Lodhi

Type of Poster: Master Intro

Advisor: Rebekka Burkholz

Title: Decoupling Model Depth from Memory Cost: Efficient LLM Fine-Tuning via Block-wise Sparsity

Research Area: RA2: Trustworthy Information Processing

Abstract: Full-parameter fine-tuning of Large Language Models (LLMs) is traditionally limited by the massive memory required to store optimizer states, which dominate the memory consumption during training. This work presents a training framework that addresses this bottleneck by combining two complementary techniques. First, Rotational Block Training updates model layers in sequential groups. This reduces the number of active parameters at any one time and enables efficient backpropagation, where the gradient calculation stops early at the active block to significantly increase training speed. Second, Sparse Optimization compresses the memory footprint of the currently active layers by storing optimizer states only for the most critical weight updates. By pairing this block-wise approach with the systematic removal of unused states for frozen layers, the framework allows for high-performance fine-tuning on memory-constrained hardware with a fraction of the VRAM required by standard methods.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Sara-Elena Vatavu

Type of Poster: Master Intro

Advisor: Michael Schwarz, Leon Trampert

Title: MaliciousFont: Exploit Font Hinting to Dynamically Change Text Content

Research Area: RA4: Threat Detection and Defenses

Abstract: Even though font rendering is ubiquitous, most people are not aware of the complexity of this process. In addition to parsing and actually drawing, characters are dynamically improved using the so-called process of hinting: the font renderer makes sure that the vector-graphic characters fit in the best possible way onto the pixel grid. To achieve that, every character can have a custom assembly-like script that adjusts the outlines. Not all formats and not all operating systems make use of hinting, but most Windows applications do. While hinting is only meant to slightly change the outline of the character to make it look as good as possible, nothing prevents an attacker from exploiting hinting to change the entire shape of a character. With that, documents that show different text depending on where they are viewed (e.g., print vs. screen) can be crafted, simply by including custom fonts. This work establishes fonts and hinting as an overlooked security vector through the systematic evaluation of hinting usage, development of a framework through which hinting instructions that visually transform one character into a different one can be generated, controlled proof-of-concept attacks and the analysis of possible mitigations.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Gunnar Heide

Type of Poster: Master Intro

Advisor: Lucjan Hanzlik

Title: VRID - A privacy-preserving digital passport for the metaverse

Research Area: RA1: Algorithmic Foundations and Cryptography

Abstract: This work aims to create a privacy-preserving system, that allows creating a verified and EUDI-Wallet compatible digital ID from any standard passport. Using a smartphone to read the passport and a web service leveraging a trusted execution environment, the system creates a SD-JWT of the passports data that allows selective disclosure during presentation from a EUDI compatible wallet. The trusted execution environment enforces that the sensitive personal data of the passport is not visible to the operator of the web service, while the passport is still verified and the created SD-JWT is signed to attest this verification. Lastly a wallet client for the Apple Vision Pro is to be created, that explores using privacy preserving credentials in AR and VR settings, while still maintaining a high level of security through hardware key binding.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Niklas Beierl

Type of Poster: Master Intro

Advisor: Ben Stock, Florian Hantke

Title: A Qualitative Look Into Ethics Boards' Assessments of Security and Privacy Research

Research Area: RA6: Empirical and Behavioural Security

Abstract: As information technology is becoming more embedded in daily life, security and privacy research is more likely to have an ethical dimension. Major publication venues are acknowledging this by increasingly requiring that authors include reflections on ethics in their work, explicitly including ethics in their review process, or requiring that submissions are approved or exempted by ethics review board or similar. There were however, several high-profile controversies about the ethical soundness of submitted works in recent years. Simultaneously, prior work has shown that ethics review is sometimes perceived as yet another bureaucratic hurdle for research projects. All in all, prior works describe the status quo as unsatisfactory. This qualitative study aims to explore the existing resources and structures that research institutions are offering to help security and privacy researchers design ethically sound research. Specifically, it will contain insights from interviews with review board members and a desk review of other resources.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Davide Bombelli

Type of Poster: Master Intro

Advisor: Abdullah Alhamdan, Alexi Turcotte, Andreas Zeller

Title: I don't understand your dialect: scalable method for compatibility study

Research Area: RA4: Threat Detection and Defenses

Abstract: The software landscape is constantly evolving, with new languages, runtimes, and libraries that promise to be in some sense compatible with existing technologies. Developers have to find a way to adapt their solutions to work on multiple interfaces. This is meant to spur adoption and migration to new technologies, but true 100% compatibility is a difficult prospect. They often rely on legacy software, and any friction can at best impede users, at worst lead to security risks if developers are not careful. In this sense, a compatibility issue can take the form of a missing property, a not exported object, an uncallable API, or simply a code misimplementation. Despite the importance of the issue, little has been done to address the problem. Compatibility studies are mainly narrowly scoped, or tied to specific platforms, making them unsuitable to solve the problem in a generalized way. In this thesis, we explore the feasibility of a new generalized approach to compatibility studies. Specifically, we take a runtime environment as ground truth, we recursively traverse all the properties of all the objects in its standard library, and try to import and call them from the second runtime environment under test. Our new method is then capable of capturing bugs both at compile time and at run time. Moreover, it does not need any external tool or software, beyond what the systems already offer in themselves. This enables compatibility analysis along multiple dimensions, including cross-runtime execution, cross-version evolution, and interoperability. We will evaluate our approach through a series of case studies that span multiple runtimes, multiple versions of the same platform, and interoperability scenarios involving different programming languages. The idea is to uncover compatibility discrepancies, including previously undocumented ones. Our preliminary results show that wrong implementation and missing properties can in practice lead to disruption of users' workflow, as well as security vulnerabilities. One of the tests we conducted has in fact found a critical vulnerability, for which we got awarded a CVE. Our results so far demonstrate the need for a unified compatibility study methodology, as it can reveal insights that are missed by conventional testing and existing tools.

 

11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Christian Boseck

Type of Poster: Bachelor Intro

Advisor: Ulysse Planta

Title: Development of an Experimentation Platform for RACCOON OS

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: As the number of satellites in orbit continues to grow, the importance of secure and reliable operating systems for these satellites increases as well. RACCOON is a project that addresses this challenge by developing a satellite system with security as a core design principle. In the context of a Capture-The-Flag (CTF) scenario, there is a strong interest in understanding how users interact with such a system and how many users attempt to establish connections to satellite-like services. However, allowing direct experimentation on the operational system is not feasible due to safety and reliability concerns. The goal of this bachelor thesis is therefore to design and implement a safe experimentation playground that allows users to connect to RACCOON-like services without affecting the operational satellite system, while still enabling the integration of monitoring and analysis mechanisms.

 

New Poster Sessions are Coming!

Written on 04.02.26 (last change on 04.02.26) by Xinyi Xu

Hey all,

The next poster session date is finalized. They are:


a. 15.04.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

So now we have 3 sessions that are ready for registration:

 

  1. 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert,… Read more

Hey all,

The next poster session date is finalized. They are:


a. 15.04.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

So now we have 3 sessions that are ready for registration:

 

  1. 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)
  2. 11.03.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)
  3. 15.04.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

The registration form (https://forms.gle/YtUfQb2N61Uo4kiP7) has been updated with the new dates. Note that there is a limit of 20 posters per session, so please register as soon as you know when you’d like to present. Also note that we are planning to hold one poster session in the break between semesters at CISPA C0; more news on that is forthcoming.

Looking forward to your participation both as a listener and/or a presenter!

Next On-Site Seminar on 14.01.2026, CISPA C0, Room 0.01

Written on 07.01.26 by Xinyi Xu

Dear All,


The next seminar(s) will take place on 14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken) - C0 Room 0.01. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person as… Read more

Dear All,


The next seminar(s) will take place on 14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken) - C0 Room 0.01. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person as well.

For presenters,
1. We would book the room half an hour in advance, so you are encouraged to arrive a few minutes early to set up your own poster.
2. For this session, you need to print the poster on your own. The size of the poster should be 116x86cm or 86x116cm. You can use the poster printing service of Saarland University (https://www.uni-saarland.de/en/page/uds-card/functions/printing.html -> Posterdruck A0).
3. You need to present your poster in a much smaller group, but you are encouraged to roam around and ask questions about other posters.
4. We encourage you to bring your laptop to present your demo; there will be small tables in the room where you can put your laptop.
 

 

Presenters: Marius Schuh, Mete Keltek, Amir Farahani Khoajseth, Piyush Pant, Niclas Dauster, Joris Hülsmann

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

Presenter: Marius Schuh

Type of Poster: Bachelor Intro

Advisor: Lorenz Hetterich

Title: Reverse-Engineering Obfuscated Virtual Machine-Based Architectures

Research Area: RA4: Threat Detection and Defenses

Abstract: Left in by accident for debugging or as backdoors installed with malicious intent, undocumented instructions can pose a significant security risk. There are Virtual Machines (VMs) implementing custom, undocumented instruction set architectures (ISAs). Malware such as FinFisher obfuscates itself by running critical code in a VM that implements a custom, undocumented ISA, hindering antivirus detection. Commercial software protection solutions like VMProtect promise software publishers robustness against cracking, reverse engineering, and debuggers for the sake of protecting intellectual property. However, this also means users cannot analyze a program’s behavior before executing it. These problems have in common the absence of publicly accessible ISA documentation. InstrSem is a novel tool that derives the semantics and encodings of unknown instructions by observing their behavior and clustering executions under different inputs. This work investigates the feasibility of integrating InstrSem into a VM to reverse-engineer its ISA.

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Mete Keltek

Type of Poster: Master Intro

Advisor: Nils Ole Tippenhauer

Title: Leveraging Agentic AI for OT Asset Discovery

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: In the current political and economic landscape, it is more important than ever to secure critical infrastructure against external threats. One such threat is a network-based attack, in which an attacker gains access to an industrial plant’s internal network and eavesdrops on traffic. Because network traffic is increasingly complex and often proprietary, attackers still face many challenges and cannot easily understand the environment. To learn about the infrastructure and identify assets of interest, they may analyze traffic to extract useful information and discover vulnerabilities. They may also leverage AI to detect patterns, thereby making the detection of OT assets and their flaws more efficient. To prepare for such attacks, industries must analyze their infrastructure for any weaknesses in the configuration of IT and OT devices. Using OT Asset Discovery software may be helpful in identifying and analyzing assets on the network. One such method used for OT asset discovery is active scanning, where the scanner actively probes the network to identify new assets. This method carries significant risk due to the potential for disrupting sensitive OT networks or devices and must be applied with caution. Using an Agentic-AI system to carry out this active scanning offers the benefit of adaptive decision-making compared to traditional rule-based scanners, but it also carries the danger of hallucinations or misinterpretations by the AI system leading to the disruption of the OT network and therefore the OT services. In our work, we aim to investigate how we can leverage an Agentic-AI system in a safe way to discover OT assets by actively scanning industrial networks. Therefore, we provide a framework that restricts the Agentic-AI system to scan only within specifically defined and allowed boundaries, which it cannot exceed, ensuring that active scans can be performed safely within the OT environment. This approach expands the capabilities of traditional active scanning in OT systems with adaptive decision-making, which ultimately results in the discovery of assets that are not discoverable with traditional methods, while also ensuring the safety of the system by preventing the Agentic-AI from sending disruptive or unwanted network requests. Beyond asset discovery, we optionally investigate whether the Agentic-AI can leverage its adaptive capabilities to identify security misconfigurations that would remain undetected by traditional rule-based scanning approaches.

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Amir Farahani Khoajseth

Type of Poster: Master Intro

Advisor: Sven Bugiel

Title: Capability-Enforced Secure Networking Architecture for Trusted Execution Environments

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: This proposal presents a secure communication architecture enabling a Trusted Execution Environment (TEE) to directly interact with network hardware while remaining isolated from a potentially compromised Rich Execution Environment (REE). The goal of the system is to ensure the integrity, confidentiality, and availability of network communication, even under full REE compromise. To achieve this, the design introduces a Capability Enforcement Module (CEM) — a hardware-based enforcement layer between the execution environments, system memory, and the network interface. The CEM verifies access capabilities in hardware, ensuring that only authorized entities can initiate network communication. In this architecture, the Trusted Firmware (TF) manages capability tokens that define the access rights of each entity, while the CAM performs on-chip verification of these capabilities for every network access request. To eliminate dependency on the untrusted REE software stack, core networking functions such as TCP/UDP are implemented directly in hardware. Once validated, the CEM retrieves the corresponding DMA descriptors and initiates secure, zero-copy data transfers between trusted memory and the network hardware. The capability system specifically targets unprivileged trusted applications, enabling them to access hardware resources directly while maintaining strict isolation from the untrusted REE. Control operations, such as capability management, occur infrequently and can be handled through (slower) hypercalls, whereas the data path allows direct, memory-mapped access between trusted applications and the hardware for low-latency performance.

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Piyush Pant

Type of Poster: Master Intro

Advisor: Xiao Zhang

Title: Stealthy Emotion-Targeted Subpopulation Attacks in RLHF

Research Area: RA2: Trustworthy Information Processing

Abstract: Reinforcement learning from human feedback (RLHF) has become the backbone of LLM alignment, yet it remains vulnerable to data poisoning and backdoor attacks. Prior methods rely on either appending an artificial backdoor trigger or heuristic clustering on a separately curated set of triggers, which limits their stealthiness and leads to non-optimal generalizability. This project aims to develop an emotion-targeted attack framework that intentionally shifts the internal representations of RLHF-aligned models by strategically contaminating a small proportion of the training data. The goal is to create natural, stealthy, and highly generalizable subpopulation attacks that more accurately reflect real-world vulnerabilities in RLHF. Through benchmarking this approach against existing baselines, we aim to provide a more principled understanding of how subtle emotion manipulations can undermine RLHF-aligned systems.

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Niclas Dauster

Type of Poster: Master Intro

Advisor: Ali Abbasi

Title: Bringing the Internet to Space: High-Performance IP over CCSDS

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: Modern satellite missions increasingly require flexible, interoperable, and high-performance communication architectures that integrate seamlessly with terrestrial network infrastructure. Implementing Internet Protocol (IP) communication over CCSDS space links offers the potential to reuse mature transport protocols, security mechanisms, and existing software ecosystems. However, space links fundamentally differ from terrestrial networks, exhibiting high and variable latency, intermittent connectivity, non-congestive bit errors, and strong uplink–downlink asymmetry, which challenge conventional IP-based transport protocols. This project aims to design and implement a standards-compliant IP-over-CCSDS communication stack for Raccoon OS, an open-source satellite operating system. The goal is to provide a transparent IP interface using CCSDS encapsulation mechanisms while maintaining compatibility with existing ground systems and space standards. A central focus of the project is the investigation of performance optimization techniques suitable for high-latency and asymmetric space links, including Performance-Enhancing Proxies (PEP/QPEP), the CCSDS Space Communications Protocol Standards Transport Protocol (SCPS-TP), and the Bundle Protocol for delay- and disruption-tolerant communication. Building on this foundation, the project follows a structured design-driven approach. An initial design phase surveys existing operational solutions, CCSDS standards, and relevant scientific literature in the areas of space-optimized transport protocols, proxy-based architectures, and delay- and disruption-tolerant networking. Based on this analysis,an architectural design is derived that balances performance, complexity, and operational constraints for IP-based communication over CCSDS links. The selected design is subsequently implemented and evaluated under emulated and mission-like space-link conditions. The evaluation focuses on key performance indicators such as throughput, latency, and reliability in the presence of high round-trip times, link asymmetry, and packet loss. The results are intended to validate the design choices and provide practical guidance for deploying high-performance IP communication in future satellite missions.

 

14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Joris Hülsmann

Type of Poster: Master Intro

Advisor: Wouter Lueks, Sylvain Chatel

Title: Privacy-by-Design Usage Analytics Architecture for the Deutschlandticket

Research Area: RA2: Trustworthy Information Processing

Abstract: The introduction of the Deutschlandticket established a nationwide flat fare for public transport in Germany, fundamentally changing revenue allocation among hundreds of transport operators. Existing revenue-sharing mechanisms for the Deutschlandticket rely on metrics such as ticket point of sale or residence-based allocation, which inadequately reflect actual usage and have led to persistent distributional disputes. A transition toward usage-based revenue sharing requires detailed usage statistics, yet conventional data collection approaches, such as continuous location tracking, pose significant privacy and security risks. This thesis presents the design and analysis of a privacy-by-design usage analytics architecture that enables the computation of passenger-kilometers per transit line for revenue sharing, without exposing individual travel behavior.

 

Next On-Site Seminar on 19.11.2025, CISPA D1 Room 0.15

Written on 12.11.25 (last change on 13.11.25) by Xinyi Xu

Dear All,


The next seminar(s) will take place on 19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany) - D1 Room 0.15. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person… Read more

Dear All,


The next seminar(s) will take place on 19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany) - D1 Room 0.15. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person as well.

For presenters,
1. We would book the room half an hour in advance, so you are encouraged to arrive a few minutes early to set up your own poster.
2. For this session, you need to print the poster on your own. The size of the poster should be 116x86cm or 86x116cm. You can use the poster printing service of Saarland University (https://www.uni-saarland.de/en/page/uds-card/functions/printing.html -> Posterdruck A0).
3. You need to present your poster in a much smaller group, but you are encouraged to roam around and ask questions about other posters.
4. We encourage you to bring your laptop to present your demo; there will be small tables in the room where you can put your laptop.
 

 

Presenters: Marco Spies, Franziska Granzow, Altaf Shaikh, Alexandre Dugast, Arina Hallemans, Wojciech Kopański, Anupam Varshney, Nils Bernsdorf, Florian Romann, Manar Mohamed

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

Presenter: Marco Spies

Type of Poster: Bachelor Intro

Advisor: Nils Ole Tippenhauer

Title: HaLLM: Leveraging LLM Agents for Automated Rehosting

Research Area: RA4: Threat Detection and Defenses

Abstract: Firmware analysis plays a central role in ensuring the security and reliability of embedded systems, which are increasingly present in critical domains ranging from consumer electronics to industrial and medical applications. Dynamic analysis of firmware binaries has become an important method to uncover vulnerabilities. However, this process is hampered by the inherent diversity, complexity, and hardware-firmware coupling characteristic of embedded systems. Emulation-based rehosting is a promising approach to these challenges. By enabling firmware execution on virtual hardware, it facilitates larger-scale testing and deeper inspection compared to the resource-constrained physical devices. A commonly adopted method in this area is abstraction layer emulation, where hardware abstraction layer (HAL) functions are substituted with high-level software models. This technique helps to overcome environmental dependencies and peripheral interactions but still requires manual creation of these models, which is time-consuming and demands specialized expertise. In this thesis, we propose to explore the use of Large Language Models (LLMs) to assist in the automation of HAL-based rehosting. The idea is that, instead of relying solely on human analysts to manually design high-level replacements for hardware interactions, LLM agents could be employed to automatically generate the corresponding abstractions. By integrating LLM-driven automation into the rehosting pipeline, we aim to reduce manual effort, enhance scalability, and ultimately lower the barrier to systematic testing and security analysis.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Franziska Granzow

Type of Poster: Master Intro

Advisor: Nils Ole Tippenhauer, Ali Abbasi

Title: Fuzzing Embedded Systems with Power Side-Channels Using Low-Cost Measurement Devices

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: Embedded systems are widely deployed in critical domains, making their security and reliability essential. Fuzzing is a powerful technique for detecting vulnerabilities, but in embedded systems, traditional feedback mechanisms such as code coverage are difficult to obtain due to hardware constraints or the lack of source code. Recent research has explored the use of power side-channel information as an alternative feedback source. However, existing approaches often rely on expensive equipment or highly controlled environments, limiting their practical applicability. In this work, we investigate whether low-cost measurement devices, such as ChipWhisperer, can effectively capture side-channel information to guide a fuzzer for real-world embedded systems. In addition to black-box fuzzing, we consider grey-box scenarios to assess the role of additional contextual information to improve fuzzing feedback.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Altaf Shaikh

Type of Poster: Master Intro

Advisor: Doreen Riepel, Nico Döttling

Title: Modularizing the Double Ratchet: Tight Security Bounds

Research Area: RA1: Algorithmic Foundations and Cryptography

Abstract: We study the security of the Double Ratchet which is the core key-evolution mechanism used by Signal. Prior work [CRT24] established tight composition bounds for a multi-user Double Ratchet by modelling the PRF-PRNG as a random oracle. This thesis aims to remove that idealization: following the modular decomposition of [ACD19], we treat the Double Ratchet as the composition of a continuous key-agreement (CKA) scheme, a PRF-PRNG, and a forward-secure AEAD (FS-AEAD), and we will preserve the intended CKA and FS-AEAD security properties while replacing the PRF-PRNG random-oracle model with a standard-model multi-user abstraction. Concretely, we will (i) formalize a multi-user security definition that captures the interaction aspects needed for tight reductions, (ii) adapt and extend the modular proof techniques used in [ACD19, CRT24], and (iii) apply reduction techniques similar to those in [BSJ+17, Appendix A] to obtain tight (or provably near-tight) bounds. As a first step we focus on the one-session / two-party case to isolate the key technical challenges, then generalize to the full multi-user setting. Secondary directions include relating our abstraction to PRF-ODH-style assumptions and investigating implications for related ratchet designs (e.g., Triple Ratchet). The expected outcome is a modular, standard-model security statement for the Double Ratchet with explicit concrete bounds, reducing reliance on random-oracle heuristics and strengthening the theoretical foundations of secure instant-messaging protocols.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Alexandre Dugast

Type of Poster: Master Intro

Advisor: Srishti Gupta, Lea Schönherr

Title: Security Assessment of Multi-Agent Systems Leveraging MCP: A Prompt Injection Perspective

Research Area: RA4: Threat Detection and Defenses

Abstract: Multi-agent systems (MAS) built on large language models represent a novel and increasingly capable approach to task automation. These systems enable specialised agents to collaborate through shared memory and dynamic tool integration. The Model Context Protocol (MCP) facilitates structured communication between agents and external tools or data sources, enabling context-aware interactions and modular orchestration. While combining MAS with MCP provides access to external resources such as files, calendars and web content, allowing for flexible and scalable orchestration, it also introduces architectural complexity and new security risks, particularly from injection attacks that exploit the agents' susceptibility to embedded instructions. This work focuses on answering the following question: how do injection attacks propagate across agents in a multi-agent setting, potentially leading to systemic compromise? This thesis explores the vulnerability of MCP-enabled MAS to injection attacks, including: a) indirect injection via malicious web content; b) tool poisoning through manipulated MCP-integrated tool metadata; and c) multi-turn injection chains. Using a LangGraph-based testbed, the thesis aims to analyse attack interactions and propagation. This will contribute to a deeper understanding of vulnerabilities in MAS architectures and inform future mitigation strategies.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Arina Hallemans

Type of Poster: Master Intro

Advisor: Laura Plein

Title: Privacy-Preserving Synthetic Data Generation combining Fuzzing with Machine Learning

Research Area: RA4: Threat Detection and Defenses

Abstract: Machine learning models are increasingly applied in various sensitive domains such as healthcare, finance, and insurance. These models often need to be trained on data containing personally identifiable information or sensitive attributes, which raises significant privacy concerns. In critical domains, it is also essential to thoroughly test models under realistic conditions to ensure their reliability. However, testers typically do not have access to the original datasets, as these are usually restricted due to confidentiality and data protection requirements. Sharing data not only enables training machine learning models and testing models in critical domains but also drives knowledge development in research and allows collaboration across organizations. However, as data sharing introduces privacy concerns and is strictly constrained by legal regulations such as the GDPR in the EU we need a solution that provides a balance between preserving the privacy and maintaining the utility of the data. Traditional anonymization techniques have been shown to be vulnerable to re-identification attacks, especially if the attacker has access to additional information. In contrast, privacy-preserving synthetic data holds better on privacy promises, such as reducing the risk of membership or attribute inference attacks, and thus enables realistic testing without exposing sensitive information. Despite these advantages it poses a greater challenge in terms of data usability. The goal of this work is to present a privacy-preserving synthetic data generator that aims to maintain the syntactic and semantic characteristics of the original dataset while minimizing privacy risks. The proposed method combines fuzzing techniques with machine learning approaches to iteratively improve the quality of the generated data. The generator creates synthetic data without accessing the original dataset, reducing the risk of direct data leakage.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Wojciech Kopański

Type of Poster: Master Intro

Advisor: Sven Bugiel

Title: Studying Android Passkey Implementations in the Wild

Research Area: RA6: Empirical and Behavioural Security

Abstract: Despite the growing industry push for passkeys – the most promising passwordless authentication method, their adoption remains limited. The existing research works have examined the prevalence of passkeys in popular websites and investigated the obstacles developers face when implementing passkey authentication. However, the integration of passkeys within the mobile space remains unexplored. This work proposes an empirical study of passkey implementation by conducting a quantitative analysis of Android applications employing them, as well as investigating the unique possible implementation methods. Additionally, the study aims to evaluate the relevant third-party services and guidelines for mobile developers.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Anupam Varshney

Type of Poster: Bachelor Intro

Advisor: Lea Schönherr, David Pape

Title: Effects of Quantization on Attacks Against Large Language Models

Research Area: RA4: Threat Detection and Defenses

Abstract: Post-training quantization enables memory- and latency-efficient deployment of large language models (LLMs), yet its security implications remain underexplored. This work presents a systematic, comprehensive study on how common 4-bit weight-only quantization schemes influence LLM robustness under realistic attack scenarios. We evaluate five quantized variants of Llama-3.2 3B (BnB-4bit, AWQ, HQQ, GPTQ, and SmoothQuant) across diverse attack types aligned with the OWASP LLM risk framework: Prompt Manipulation, Alignment-Breaking, and Evasion & Robustness attacks. Experiments include black-box attacks (PWWS, AutoDAN, Indirect Prompt Injection, Prompt Injection, Prompt-Extraction) and a white-box gradient-based jailbreak (GCG). Our findings reveal that quantization reshapes rather than uniformly reduces vulnerabilities: AWQ stabilizes activations, preserving semantics; GPTQ and SmoothQuant weaken gradient-based attacks through weight rounding or activation smoothing; while prompt-leakage attacks largely persist. To capture robustness changes quantitatively, we propose the Quantization Sensitivity Score (QSS), measuring per-attack robustness shifts relative to the full-precision baseline. Finally, we link QSS with task utility (MMLU, GSM8K) for comparison, SmoothQuant achieves near-baseline accuracy (MMLU 61.4, GSM8K 75.5) while maintaining moderate QSS (7.3 pp), offering the best balance between efficiency, utility, and security.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Nils Bernsdorf

Type of Poster: Master Intro

Advisor: Michael Schwarz

Title: Efficient Instruction Sequence Generation for Fuzzing Closed-Source CPUs using Reinforcement Learning

Research Area: RA4: Threat Detection and Defenses

Abstract: Hardware fuzzing has been demonstrated to be an effective technique for discovering security vulnerabilities in both open- and closed-source CPU designs. However, the effectiveness of a hardware fuzzer greatly depends on its ability to generate instruction sequences that trigger a diverse set of microarchitectural events within the CPU. To achieve this, state-of-the-art fuzzers for open-source CPU designs commonly make use of Register Transfer Level (RTL) coverage as a feedback mechanism to guide instruction selection. However for closed-source commercial CPUs, where such coverage information is unavailable, existing fuzzers often do not rely on any feedback mechanism and instead choose instructions according to a simple static policy. This thesis aims to address this shortcoming by developing a novel sequence generation approach for fuzzing closed-source CPUs. Lacking a precise coverage metric, we propose to use hardware debug interfaces such as performance counters to observe certain microarchitectural events within the CPU. We hypothesize that increasing the frequency of these events, will trigger more microarchitectural edge cases and therefore reduce the time until a bug is found. Due to the highly temporal and sparse nature of the performance counter increments, we propose to model sequence generation as a Reinforcement Learning (RL) task, where in each step the RL agent receives an observation of the processor's current state and selects the next instruction to execute. The agent is then guided towards maximizing the performance counters by giving a reward every time a counter is incremented.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Florian Romann

Type of Poster: Master Intro

Advisor: Eric Ackermann, Sven Bugiel

Title: Navigating the Sea of Options: Exploring Compile-Time Configuration Fuzzing for Zephyr

Research Area: RA5: Secure Mobile and Autonomous Systems

Abstract: Embedded devices are everywhere, from consumer electronics to automotive and industrial monitoring systems. Zephyr, a real-time operating system supporting over 800 hardware platforms, handles this diversity through over 8400 configuration options. To ensure the security of Zephyr and its boards, Zephyr's configurability must be considered when testing. Recent advances in configuration fuzzing have discovered over 500 bugs in configurable sofware. However, these approaches target runtime configurations that can be fully tested using one binary, but Zephyr's configurability is set at compile-time, resulting in a distinct binary for every configuration. This fragmentation scatters coverage feedback across configurations and requires recompilation for every tested configuration. This thesis presents Compass, the first compile-time configuration fuzzer for Zephyr. Compass uses Fandango to generate semantically valid configurations from Zephyr's Kconfig specification, respecting complex constraints and interdependencies. Using line coverage, Compass enables coverage tracking across multiple builds and selects configurations that maximize code exploration. Finally, the selected configurations are fuzzed on emulated hardware. Our evaluation will analyze the efficiency of the configuration generation of Compass and compare its fuzzing performance to the-state-of-the-art.

 

19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)

 

Presenter: Manar Mohamed

Type of Poster: Master Intro

Advisor: Nico Döttling

Title: New Scheme for Group Action Adaptor Signatures

Research Area: RA1: Algorithmic Foundations and Cryptography

Abstract: We propose a new Adaptor Signature scheme for generic Group Actions. An adaptor signature allows a signer to generate a pre-signature for an instance of a hard relation. Only a party that knows the witness to the instance of the hard relation can adapt the pre-signature into a full valid signature using the witness. From both the pre-signature and the signature, the signer can extract the witness. Adaptor Signatures have many applications such as atomic swaps and payment channel networks. Our work is focused on the group action setting. Starting from Joux’s MPCitH post-quantum signature framework for Group Actions, we extend his framework to construct Adaptor Signature for the group-action DLog relation. Our scheme satisfies the standard security notions of strong unforgeability, pre-signature adaptability, witness extractability, witness hiding and adapted signature unlinkability.

 

New Poster Sessions are Coming!

Written on 21.10.25 (last change on 04.02.26) by Xinyi Xu

Hey all,

The next poster session date is finalized. They are:


a. 14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)
b. 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)
c. 11.03.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123… Read more

Hey all,

The next poster session date is finalized. They are:


a. 14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)
b. 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)
c. 11.03.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

So now we have 4 sessions that are ready for registration:

1. 19.11.2025, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)
2. 14.01.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)
3. 11.02.2026, 14:00 - 16:00, CISPA D1 (Kaiserstraße 21 66386 St. Ingbert, Germany)
4. 11.03.2026, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

The registration form (https://forms.gle/YtUfQb2N61Uo4kiP7) has been updated with the new dates. Note that there is a limit of 20 posters per session, so please register as soon as you know when you’d like to present. Also note that we are planning to hold one poster session in the break between semesters at CISPA C0; more news on that is forthcoming.

Looking forward to your participation both as a listener and/or a presenter!

Next On-Site Seminar on 08.10.2025, CISPA C0 Room 0.02

Written on 02.10.25 by Xinyi Xu

Dear All,


The next seminar(s) will take place on 08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken) - CISPA C0 Room 0.02, Stuhlsatzenhaus 5, 66123 Saarbrücken. Presenters and their advisors are encouraged to present in person. We especially encourage other students and… Read more

Dear All,


The next seminar(s) will take place on 08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken) - CISPA C0 Room 0.02, Stuhlsatzenhaus 5, 66123 Saarbrücken. Presenters and their advisors are encouraged to present in person. We especially encourage other students and teachers to attend and present in person as well.

For presenters,
1. We would book the room half an hour in advance, so you are encouraged to arrive a few minutes early to set up your own poster.
2. For this session, you need to print the poster on your own. The size of the poster should be 116x86cm or 86x116cm. You can use the poster printing service of Saarland University (https://www.uni-saarland.de/en/page/uds-card/functions/printing.html -> Posterdruck A0).
3. You need to present your poster in a much smaller group, but you are encouraged to roam around and ask questions about other posters.
4. We encourage you to bring your laptop to present your demo; there will be small tables in the room where you can put your laptop.
 

 

Presenters: Peter Gastauer, Bushra Ashfaque, Malik Ali Haider Awan, Simran Kathpalia, Prerak Mittal, Bushra Ashfaque, Prerak Mittal

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

Presenter: Peter Gastauer

Type of Poster: Master Intro

Advisor: Swen Jacobs

Title: Compiling Distributed Algorithms in Pseudocode into Extended Threshold Automata

Research Area: RA3: Reliable Security Guarantees

Abstract: Extended threshold automata have proven effective in the automatic verification of fault-tolerant distributed algorithms. The first important step in verification, however, lies in the faithful translation of the algorithm into a threshold automaton. This step can be tedious and error-prone when done by hand and also requires a solid understanding of the model. To ensure correctness throughout the verification process, an accurate automatic translation is thus preferable. Earlier work proposed a computationally expensive translation from pseudocode into less expressive threshold automata, via receive threshold automata. This work improves on the state of the art by directly compiling from a pseudocode representation of a distributed algorithm into an extended threshold automaton. This would allow users to work with a commonly used format and avoid the need of an error prone manual translation.

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Bushra Ashfaque

Type of Poster: Master Intro

Advisor: Andreas Zeller, Max Eisele

Title: Automated Embedded Pentesting using Fandango and LLM Agents

Research Area: RA4: Threat Detection and Defenses

Abstract: While Large Language Model (LLM) agents have demonstrated autonomous capabilities in exploiting vulnerabilities in web applications [1], a significant research gap exists in applying these AI-driven methodologies to the unique challenges of embedded systems. These systems, critical to automotive and IoT domains, are characterized by hardware-specific interfaces, real-time constraints, and specialized protocols inaccessible to conventional AI pentesting tools. This thesis, conducted in collaboration with Robert Bosch GmbH, addresses this gap by designing, implementing, and evaluating a comprehensive framework and testbench architecture that bridges the divide between AI agents and embedded hardware, following established pentesting methodologies [2]. The core of this work is a modular testbench and a novel abstraction layer, the Model Context Protocol (MCP), enabling standardized communication with hardware interfaces like CAN and UART. We employ the Fandango fuzzing framework [3] as the primary engine for test generation and execution. By translating formal protocol specifications, such as ISO 14229-1 UDS (Unified Diagnostic Services) [4], into a stateful, executable grammar within a self-contained .fan file, we empower Fandango's engine to autonomously manage and validate complex, multi-step interactions. This is achieved by embedding Python ConnectParty classes directly within the grammar, allowing Fandango to orchestrate the entire test flow from generation to response validation. The methodology will be validated using an ESP32 microcontroller, where this framework will be used to pentest a sample UDS implementation and evaluate its security features, such as secure boot and flash encryption. The ultimate goal of this thesis is to create a complete, automated pentesting pipeline that takes system specifications and security goals as input, generates a formal test plan as a Fandango grammar, executes a comprehensive fuzzing campaign against the target hardware, and leverages an LLM to generate a final, structured vulnerability report from the factual test results. This research will deliver a novel, open-source architecture for AI-assisted embedded security and provide empirical insights into its effectiveness in identifying protocol violations and security flaws in real-world embedded systems. References [1] R. Fang, R. Bindu, A. Gupta, Q. Zhan, and D. Kang. LLM Agents can Autonomously Exploit One-day Vulnerabilities. arXiv preprint arXiv:2404.08144, 2024. [2] OWASP Foundation. OWASP Web Security Testing Guide v4.2. 2021. Available: https://owasp.org/www-project-web-security-testing-guide/ [3] https://fandango-fuzzer.github.io/ [4] https://drive.google.com/file/d/1tZzNG2Dz3EGsmsdWdHP5Z98Z3YrD9BGT/view?usp=sharinghttps://drive.google.com/file/d/1tZzNG2Dz3EGsmsdWdHP5Z98Z3YrD9BGT/view?usp=sharing

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Malik Ali Haider Awan

Type of Poster: Master Intro

Advisor: Rafael Dutra, Andreas Zeller

Title: LEARNING FORMAT CONSTRAINTS FOR ENHANCED FUZZING

Research Area: RA4: Threat Detection and Defenses

Abstract: This thesis proposes learning-based enhancement to FormatFuzzer to automatically discover and integrate format constraints—such as magic numbers and chunk identifiers—from valid sample files. By incorporating these learned constraints either manually or dynamically during fuzzing, the approach aims to significantly increase the validity of generated inputs and improve fuzzing effectiveness.

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Simran Kathpalia

Type of Poster: Master Intro

Advisor: Christian Rossow, Marcel Böhme

Title: Efficient Software-Based Memory Tagging

Research Area: RA4: Threat Detection and Defenses

Abstract: Memory safety vulnerabilities represent one of the most critical security challenges in modern software systems. Despite decades of research and deployment of various mitigation techniques, C and C++ programs remain susceptible to memory corruption attacks such as buffer overflows, use-after-free, and unitialized memory. Memory tagging has emerged as a promising defense mechanism, enabling the detection of illegal memory operations at runtime by associating lightweight metadata, or “tags,” with both pointers and memory allocations. When implemented in hardware, such as in ARM’s Memory Tagging Extension (MTE), SPARC’s Application Data Integrity (ADI) and now Apple's recent Memory Integrity Enforcement (MIE), demonstrate comprehensive protection with minimal overhead (<5%). However, the dominant x86 architecture lacks native hardware support for memory tagging, motivating software-based solutions such as xTag and Stickytags. While software approaches can achieve broad memory safety coverage, they incur substantial runtime and memory overhead, limiting their practicality in real-world deployments. This thesis investigates how to make software-based memory tagging on x86 efficient without compromising security guarantees. The main focus is on identifying the dominant sources of overhead in current schemes. Based on the results we intent to design a partial tagging scheme, reducing the performance without undermining security. By combining selective tagging with complementary hardware defenses, it may be possible to approximate the strong protections of hardware memory tagging while significantly reducing performance costs. This research seeks to make software memory tagging on x86 both practical and efficient, bridging the gap between hardware-supported security guarantees and deployable software defenses.

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Prerak Mittal

Type of Poster: Master Intro

Advisor: Aleksei Stafeev, Giancarlo Pellegrino

Title: e-BOLA Screening: Backtracking Object Lineage In Web APIs To Detect Authorization Issues

Research Area: RA6: Empirical and Behavioural Security

Abstract: Modern web applications are increasingly architected around APIs, a design choice that, despite its benefits, often leads to severe authorization vulnerabilities like Broken Object Level Authorization (BOLA). Traditional methods for identifying BOLA flaws are constrained by their reliance on static documentation (e.g., OpenAPI) or manual penetration testing, rendering them unscalable and inadequate for dynamic application environments. Robust BOLA detection requires a deep understanding of the logical connections between data objects managed by the API, unlike generic fuzzing. This thesis introduces a novel LLM-assisted black-box approach that automates the discovery of these relationships. By analyzing live traffic, our system reconstructs the object lineage, inferring dependencies and hierarchies between disparate API entities. This data model is then leveraged to generate test-cases and fuzz the API to uncover hidden authorization flaws.

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Bushra Ashfaque

Type of Poster: Master Intro

Advisor: Max Eisele, Andreas Zeller, Alexander Liggesmeyer

Title: Penetration Testing on Embedded Systems using Fandango Constraints

Research Area: RA4: Threat Detection and Defenses

Abstract: Connected devices increasingly rely on standardized protocols to enable remote maintenance, configuration, and updates. Across domains such as IoT, industrial control, and automotive, many authentication mechanisms depend on the unpredictability of random values such as seeds, nonces, or challenges. If these values are predictable or biased, attackers can bypass protections and gain unauthorized access. We propose a grammar-based fuzzing framework built on the Fandango engine that integrates NIST randomness tests into protocol testing. The framework generates valid diagnostic sequences, evaluates challenge values in real time, and adapts its strategy when weaknesses are detected. Our case study is the Unified Diagnostic Services (UDS) protocol SecurityAccess mechanism, where Electronic Control Units (ECUs) issue authentication seeds that must resist prediction. The results include a reusable fuzzing- and-analysis toolchain, empirical insights into seed unpredictability, and recommendations for robust random number generation. Beyond automotive security, this approach provides a general methodology for testing any protocol whose authentication relies on high-quality randomness.

 

08.10.2025, 14:00 - 16:00, CISPA C0 (Stuhlsatzenhaus 5, 66123 Saarbrücken)

 

Presenter: Prerak Mittal

Type of Poster: Master Intro

Advisor: Aleksei Stafeev, Giancarlo Pellegrino

Title: e-BOLA Screening: Backtracking Object Lineage In Web APIs To Detect Authorization Issues

Research Area: RA6: Empirical and Behavioural Security

Abstract: Modern web applications are increasingly architected around APIs, a design choice that, despite its benefits, often leads to severe authorization vulnerabilities like Broken Object Level Authorization (BOLA). Traditional methods for identifying BOLA flaws are constrained by their reliance on static documentation (e.g., OpenAPI) or manual penetration testing, rendering them unscalable and inadequate for dynamic application environments. Robust BOLA detection requires a deep understanding of the logical connections between data objects managed by the API, unlike generic fuzzing. This thesis introduces a novel LLM-assisted black-box approach that automates the discovery of these relationships. By analyzing live traffic, our system reconstructs the object lineage, inferring dependencies and hierarchies between disparate API entities. This data model is then leveraged to generate test-cases and fuzz the API to uncover hidden authorization flaws.

 

Winter is Coming

Written on 01.10.25 by Xinyi Xu

Dear all,

Welcome to the new course for the Bachelor and Master seminar in the winter term.
Please switch to this course.

Best wishes,

BAMA Seminar Team

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