Computer Architecture

Paper List

• ``Runahead Execution: An Alternative to Very Large Instruction Windows for Out‑of‑Order Processors,'' Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt, in HPCA, 2003. (https://cms.cispa.saarland/comparch_s26/dl/27/Mutlu2003Runahead.pdf)
• ``Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems,'' Thomas Moscibroda and Onur Mutlu, in USENIX Security, 2007. (https://cms.cispa.saarland/comparch_s26/dl/28/Mutlu2007Memory.pdf)
• ``Dark Silicon and the End of Multicore Scaling,'' Hadi Esmaeilzadeh, Emily Blem, Renée St. Aman, Karthikeyan Sankaralingam, Doug Burger, in ISCA, 2011. (https://cms.cispa.saarland/comparch_s26/dl/10/Esmaeilzadeh2011Dark.pdf)
• ``MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP,'' Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, and Yale N. Patt in MICRO, 2012. (https://cms.cispa.saarland/comparch_s26/dl/20/Khubaib2012MorphCore.pdf)
• ``FLUSH+ RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack,'' Yuval Yarom and Katrina Falkner. in USENIX Security, 2014. (https://cms.cispa.saarland/comparch_s26/dl/38/Resolution2014FLUSH_.pdf)
• ``AVATAR: A Variable-Retention-Time VRT Aware Refresh for DRAM Systems,'' Moinuddin Qureshi, Dae Hyun Kim, Samira Khan, Prashant Nair, and Onur Mutlu, in DSN 2015. (https://cms.cispa.saarland/comparch_s26/dl/37/Qureshi2015AVATAR.pdf)
• ``A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,'' Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, in ISCA, 2015. (https://cms.cispa.saarland/comparch_s26/dl/3/Ahn2015A.pdf)
• ``DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks,'' Peter Pessl, Daniel Gruss, Clementine Maurice, Michael Schwarz, Stefan Mangard, in USENIX Security, 2016. (https://cms.cispa.saarland/comparch_s26/dl/36/Pessl2016DRAMA.pdf)
• ``Sanctum: Minimal Hardware Extensions for Strong Software Isolation,'' V. Costan, I. Lebedev, und S. Devadas, in USENIX Security, 2016. (https://cms.cispa.saarland/comparch_s26/dl/9/Costan2016Sanctum.pdf)
• ``Another Flip in the Wall of Rowhammer Defenses,'' Daniel Gruss, Moritz Lipp, Michael Schwarz, Daniel Genkin, Jonas Juffinger, Sioli OConnell, Wolfgang Schoechl, Yuval Yarom in IEEE S&P, 2018. (https://cms.cispa.saarland/comparch_s26/dl/14/Gruss2018Another.pdf)
• ``Meltdown: Reading Kernel Memory from User Space,'' Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, Mike Hamburg, in USENIX Security, 2018. (https://cms.cispa.saarland/comparch_s26/dl/25/Lipp2018Meltdown.pdf)
• ``Spectre Attacks: Exploiting Speculative Execution,'' Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, Yuval Yarom, in IEEE S&P, 2019. (https://cms.cispa.saarland/comparch_s26/dl/23/Kocher2019Spectre.pdf)
• ``ZombieLoad: Cross-Privilege-Boundary Data Sampling,'' Michael Schwarz, Moritz Lipp, Daniel Moghimi, Jo Van Bulck, Julian Stecklina, Thomas Prescher, and Daniel Gruss, in CCS, 2019. (https://cms.cispa.saarland/comparch_s26/dl/40/Schwarz2019ZombieLoad.pdf)
• ``ScatterCache: Thwarting Cache Attacks via Cache Set Randomization,'' M. Werner, T. Unterluggauer, L. Giner, M. Schwarz, D. Gruss, und S. Mangard, in USENIX Security, 2019. (https://cms.cispa.saarland/comparch_s26/dl/44/Werner2019ScatterCache.pdf)
• ``Graphene: Strong yet lightweight row hammer protection.'' Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, and Jae W. Lee. in MICRO, 2020. (https://cms.cispa.saarland/comparch_s26/dl/33/Park2020Graphene.pdf)
• ``Keystone: An Open Framework for Architecting Trusted Execution Environments,'' D. Lee, D. Kohlbrenner, S. Shinde, K. Asanović, und D. Song, in EuroSys, 2020. (https://cms.cispa.saarland/comparch_s26/dl/24/Lee2020Keystone.pdf)
• ``Iceclave: A Trusted Execution Environment for In-Storage Computing,'' Luyi Kang, Yuqi Xue, Weiwei Jia, Xiaohao Wang, Jongryool Kim, Changhwan Youn, Myeong Joon Kang, Hyung Jin Lim, Bruce Jacob, and Jian Huang, in MICRO, 2021. (https://cms.cispa.saarland/comparch_s26/dl/19/Kang2021Iceclave.pdf)
• ``IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors,'' Jawad Haj-Yahya, Jeremie S. Kim, A. Giray Yağlıkçı, Ivan Puddu, Lois Orosa, Juan Gómez-Luna, Mohammed Alser, Onur Mutlu, in ISCA, 2021. (https://cms.cispa.saarland/comparch_s26/dl/15/Haj-Yahya2021IChannels.pdf)
• ``Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory'' Jisung Park, Roknoddin Azizi, Geraldo F. Oliveira, Mohammad Sadrosadati, Rakesh Nadig, David Novo, Juan Gómez-Luna, Myungsuk Kim, and Onur Mutlu, in MICRO, 2022. (https://cms.cispa.saarland/comparch_s26/dl/34/Park2022Flash-Cosmos.pdf)
• ``Reliability-Aware Runahead,'' Ajeya Naithani, Lieven Eeckhout, in HPCA 2022. (https://cms.cispa.saarland/comparch_s26/dl/30/Naithani2022Reliability-Aware.pdf)
• ``RowPress: Amplifying Read Disturbance in Modern DRAM Chips,'' Haocong Luo, Ataberk Olgun, A. Giray Yağlıkçı, Yahya Can Tuğrul, Steve Rhyner, M. Banu Cavlak, Joel Lindegger, Mohammad Sadrosadati, Onur Mutlu, in ISCA, 2023. (https://cms.cispa.saarland/comparch_s26/dl/26/Luo2023RowPress.pdf)
• ``SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling,'' Minbok Wi, Jaehyun Park, Seoyoung Ko, Michael Jaemin Kim, Nam Sung Kim, Eojin Lee, Jung Ho Ahn, in HPCA, 2023. (https://cms.cispa.saarland/comparch_s26/dl/45/Wi2023SHADOW.pdf)
• ``Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks,'' L. Giner, S. Steinegger, A. Purnal, M. Eichlseder, T. Unterluggauer, S. Mangard, und D. Gruss, in IEEE S&P, 2023. (https://cms.cispa.saarland/comparch_s26/dl/13/Giner2023Scatter.pdf)
• ``Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations,'' Hasan Hassan, Ataberk Olgun, A. Giray Yağlıkçı, Haocong Luo, Onur Mutlu, in MICRO, 2024. (https://cms.cispa.saarland/comparch_s26/dl/16/Hassan2024Self-Managing.pdf)
• ``Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis,'' İsmail Emir Yüksel, Yahya Can Tuğrul, Ataberk Olgun, F. Nisa Bostancı, A. Giray Yağlıkçı, Geraldo F. Oliveira, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu, in HPCA, 2024. (https://cms.cispa.saarland/comparch_s26/dl/46/Yueksel2024Functionally-Complete.pdf)
• ``MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing,'' Geraldo F. Oliveira, Ataberk Olgun, A. Giray Yağlıkçı, F. Nisa Bostancı, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu, in HPCA, 2024. (https://cms.cispa.saarland/comparch_s26/dl/32/Oliveira2024MIMDRAM.pdf)
• ``Cascade: CPU Fuzzing via Intricate Program Generation,'' F. Solt, K. Ceesay-Seitz, und K. Razavi, in USENIX Security, 2024. (https://cms.cispa.saarland/comparch_s26/dl/42/Solt2024Cascade.pdf)
• ``RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing,'' F. Thomas, L. Hetterich, R. Zhang, D. Weber, L. Gerlach, und M. Schwarz, in CCS, 2024. (https://cms.cispa.saarland/comparch_s26/dl/43/Thomas2024RISCVuzz.pdf)
• ``Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance,'' Oğuzhan Canpolat, A. Giray Yağlıkçı, Geraldo F. Oliveira, Ataberk Olgun, F. Nisa Bostancı, Ismail Emir Yüksel, Haocong Luo, Oğuz Ergin, Onur Mutlu, in HPCA, 2025. (https://cms.cispa.saarland/comparch_s26/dl/8/Canpolat2025Chronus.pdf)
• ``ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems,'' İsmail Emir Yüksel, Ataberk Olgun, F. Nisa Bostancı, Haocong Luo, A. Giray Yağlıkçı, Onur Mutlu, in MICRO, 2025. (https://cms.cispa.saarland/comparch_s26/dl/47/Yueksel2025ColumnDisturb.pdf)
• ``Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses,'' F. Nisa Bostancı, Oğuzhan Canpolat, Ataberk Olgun, İsmail Emir Yüksel, Konstantinos Kanellopoulos, Mohammad Sadrosadati, A. Giray Yağlıkçı, Onur Mutlu, in MICRO, 2025. (https://cms.cispa.saarland/comparch_s26/dl/5/Bostanc_2025Understanding.pdf)
• ``PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips,'' İsmail Emir Yüksel, Akash Sood, Ataberk Olgun, Oğuzhan Canpolat, Haocong Luo, F. Nisa Bostancı, Mohammad Sadrosadati, A. Giray Yağlıkçı, Onur Mutlu, in ISCA, 2025. (https://cms.cispa.saarland/comparch_s26/dl/48/Yueksel2025PuDHammer.pdf)
• ``PreFence: A Fine-Grained and Scheduling-Aware Defense Against Prefetching-Based Attacks,'' Till Schlüter, Nils Ole Tippenhauer, in EuroS&P, 2025 (https://cms.cispa.saarland/comparch_s26/dl/39/Schlueter2025PreFence.pdf)
• ``Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems,'' P. C. Kocher, in CRYPTO, 1996. (https://cms.cispa.saarland/comparch_s26/dl/22/Kocher1996Timing.pdf)
• ``Dynamic Branch Prediction with Perceptrons,'' Daniel A. Jiménez, Calvin Lin, in HPCA, 2001. (https://cms.cispa.saarland/comparch_s26/dl/17/Jim_nez2001Dynamic.pdf)
• ``Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,'' Moinuddin K. Qureshi Yale N. Patt, in MICRO, 2006. (https://cms.cispa.saarland/comparch_s26/dl/35/Patt2006Utility-Based.pdf)
• ``Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,'' Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, und O. Mutlu, in ISCA, 2014. (https://cms.cispa.saarland/comparch_s26/dl/21/Kim2014Flipping.pdf)
• ``Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,'' Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, and Todd C. Mowry, in MICRO, 2017. (https://cms.cispa.saarland/comparch_s26/dl/41/Seshadri2017Ambit.pdf)
• ``A Modern Primer on Processing in Memory,'' O. Mutlu, S. Ghose, J. Gómez-Luna, und R. Ausavarungnirun, in Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann, Springer, 2022. (https://cms.cispa.saarland/comparch_s26/dl/29/Mutlu2022A.pdf)
• ``TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities,'' R. Kande, A. Crump, G. Persyn, P. Jauernig, A.-R. Sadeghi, A. Tyagi, und J. Rajendran, in USENIX Security, 2022. (https://cms.cispa.saarland/comparch_s26/dl/18/Kande2022TheHuzz.pdf)
• ``DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,'' Ataberk Olgun, Hasan Hassan, A. Giray Yağlıkçı, Yahya Can Tuğrul, Lois Orosa, Haocong Luo, Minesh Patel, Oğuz Ergin, Onur Mutlu, TCAD, 2023. (https://cms.cispa.saarland/comparch_s26/dl/31/Olgun2023DRAM.pdf)
• ``Enabling Low-Cost Secure Computing on Untrusted In-Memory Architectures,'' Sahar Ghoflsaz Ghinani, Jingyao Zhang, Elaheh Sadredini, in USENIX Security, 2025. (https://cms.cispa.saarland/comparch_s26/dl/12/Ghinani2025Enabling.pdf)
• ``Memory Band-Aid: A Principled RowHammer Defense-in-Depth,'' Carina Fiedler, Jonas Juffinger, Sudheendra Raghav Neela, Martin Heckel, Hannes Weissteiner, A. Giray Yağlıkçı, Florian Adamsky, Daniel Gruss, in NDSS, 2026. (https://cms.cispa.saarland/comparch_s26/dl/11/Fiedler2026Memory.pdf)